D flip-flop with asynchronous set/reset (top), compared to a D-FF without set/reset (bottom). The major change is replacing the inverters with NAND gates.

On the ARM Cortex-M3 96MHz mbed, I was able to SPI write out 3456 bits of data at 1.6kHz — plus some integer math and memory look-up time. How fast is the XMOS, where each core is clocked at 400MHz, four times the speed of the mbed? Here’s my XMOS code, which does SPI writes in 32-bit chunks. There is no hardware peripheral specifically for SPI, so you have to make use of their buffered I/O ports.

I clocked it at 2.5kHz (108 transfers of 32-bits), which isn’t that much faster than my mbed code. The mbed had serial at 16MHz, but the XMOS code is 12.5MHz, so the comparison isn’t 100% fair. Below is the main code that writes out data. Note that the XMOS has to do some extra work for each transfer. Reconfiguring the port seems to take around 1 us, which is a waste of time.

Of course, the majority of the time is spent in the serial transfer itself. If there were absolutely no overhead, the maximum transfer rate would have been 12.5MHz / 3456 = 3.61kHz. The nature of XMOS buffered I/O and SPI mode 0 adds around 30% overhead.

void send_word(unsigned int data) {
	//check MSB of data and set MOSI line accordingly
	//skip check if you need SPI mode 3, and set clock pattern to 0xFFFFFFFF

	if (data & 0x80000000)
		configure_out_port(mosi, blk2, 1);
	else
		configure_out_port(mosi, blk2, 0);

	//reverse data to big endian order
	mosi <: (bitrev(data) >> 1);

	//clock pattern
	sclk <: 0x55555555;
	sclk <: 0x55555555;
	// wait until clocked output operation is finalized.
	sync(sclk);
}

I’ve given up on my high-speed ADC interface project because I’m unfamiliar with Verilog and don’t have the time to learn it well enough to do an actual real, complex design. Besides, to do anything useful, like interface with a computer via Ethernet or USB, requires a softcore CPU to handle the high-level protocol details that would be painful to implement in HDL. Then, I’d have to create some sort of bridge interface between the high speed ADC and the processor bus. Then, I’d have to do some embedded development for the processor, which is another toolchain to set up and figure out. That’s a pretty big PITA when all I really wanted to do was to try to produce a hobbyist board with a 780-pin BGA and put the signal integrity knowledge I have into practice.

I’d ask my classmates, who all seem to be pursuing digital, but we’re all pretty swamped with our own work. Besides, there probably isn’t a market for some development board with 8GB of ram connected to a cheap $50 – $200 FPGA anyway.

Lately I’ve been getting into analog IC design. Soon I’ll have to choose between pursuing a more academic path and spending an extra year to make time for research projects, or just graduating in four years and pursuing a career in general PCB-level system design. It seems like the latter is way more accessible and easier. However, it seems like there’s limited potential in that career path compared to doing IC design.

Unfortuntely, the low-end Xilinx Spartan-6 FPGA’s do not support interfacing to DIMMs:

Which means that for practical purposes, the memory storage size will be limited to 512MB (2x 2Gbit memory chips). To interface with DIMM’s, which contain 8 or 16 of these chips, you’d have to go to their Virtex line for which the cheapest is at least $200, too expensive for me.

But Altera’s low-end Cyclone FPGA’s do support DIMM’s. Vendor switching time! Probably should have done some more research before plopping down money for the Digilent Atyls board, but it’s pretty feature packed and could be handy to have around for the future anyway.

Two RGB sticks daisy chained together, total of 16″.