06
May
11

CMOS Op-Amp Design

Here’s a two-stage op-amp I designed for an undergraduate class. Fun times.

Spec Vcm = -0.1V Vcm = 0V Vcm = 0.1V
Open Loop DC Gain > 5000 V/V 5130 V/V 5074 V/V 4996 V/V
Unity Loop Gain Freq. > 10 MHz 10.89MHz 11.0MHz 11.07MHz
Loop Gain Phase Margin > 60° 60.48° 60.25° 60.09°
Input Offset Voltage < 3 mV 11.91uV -3.943uV -15.89uV
Slew Rate Positive > 10 V/us 56.24 V/us 59.34 V/us 56.11 V/us
Slew Rate Negative < -10 V/us -10.2 V/us -10.18 V/us -10.17 V/us
Output Swing Low -300mV -598mV -586mV -545mV
Output Swing High 300mV 497mV 557mV 554mV

 

Current 96.26 uA
Power 115.5 uW
Area 46.68 um^2
Compensation Cap 0.13 pF
Figure of Merit 1.427



2 Responses to “CMOS Op-Amp Design”


  1. 1 kiran Oct 7th, 2011 at 6:33 pm

    Is that cadence design??

  2. 2 Clem Oct 19th, 2012 at 8:15 pm

    Doe this really work? can you share the layout design?

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